1. Field of Invention
The present invention relates to a computer having error correction and detection (EDC) circuitry. More particularly, the invention relates to an apparatus and method for testing memory storage bits associated with check bits, without interfering with the operation of EDC circuitry.
2. Description of Related Art
EDC circuitry helps computers operate with increased accuracy and efficiency, and may even prevent certain computer malfunctions. Accordingly, EDC circuitry has become an integral part of today's computers.
A typical system that utilizes EDC is shown in FIG. 1. In a typical write operation, the EDC circuitry 100 receives input data from a central processing unit (CPU) bus 102. The data on the bus 102 comprises a multi-bit data word. Based upon the data word, the EDC circuitry 100 calculates a set of check bits. The check bits are calculated using one of a variety of checking routines, many of which are well known in the art.
In a write operation of a typical computer, the EDC circuitry 100 writes the data word bits to a random access memory 104, via a data bus 106. Likewise, the EDC circuitry 100 writes the set of check bits to the memory 104, via a check bus 108. Each address of the memory 104 is shown in FIG. 1 as a horizontal row. For each address of the memory 104, the storage bits in which the data word bits can be written are designated as 110; the storage bits in which the check bits can be written are designated as 112. The address in which the data word bits and the check bits are stored is designated by an address input, received by the memory 104 via an address bus 114.
In a typical read operation, the EDC circuitry receives the data word bits from the memory 104, and supplies these bits to the CPU bus 102. More specifically, in a single read operation, the EDC circuitry 100 receives the data word bits from the storage bits 110, via the data bus 106. Additionally, the EDC circuitry receives the set of check bits from the storage bits 112, via the check bus 108.
Various testing schemes have been used to indirectly test the memory 104. One scheme involves directly testing the memory 104 by writing user-selected data to the memory 104, and reading the data from the memory 104 to determine whether the memory 104 properly stored the data. The test can be easily performed for the storage bits 110, by simply instructing the CPU (not shown) to supply the EDC circuitry 100 with the desired data word bits. However, it is more difficult to test the storage bits 112, since it is troublesome to write user-selected check bits to the memory 104.
One method used to test the storage bits 112 uses "diagnostic and visibility" registers (not shown) that are embedded within EDC control logic of some models of computers. Testing the storage bits 112 involves a number of steps. First, the desired check bits are written into a particular diagnostic register, and a diagnostic write operation is performed, which writes the contents of the diagnostic register into the storage bits 112. Next, a read operation is performed, which places the contents of the storage bits 112 into the diagnostic register. Then, the contents of the diagnostic register are compared to the check bits that were originally written into the diagnostic register. Although this method accomplishes the result of testing the storage bits 112, it is still considered inadequate in some applications. Specifically, since the steps outlined above occupy the central processor for some period of time, the overall operation of the computer is slowed. Furthermore, during the diagnostic test, the error detecting and correcting circuitry 100 is effectively disabled.
An alternative method that been used to test the storage bits 112 involves calculating the data word bits which, when input into the EDC circuitry 100, produce a pattern of check bits that is designed to test the storage bits 112. When the calculated data word bits are placed on the CPU bus 102, the EDC circuitry 100 generates the desired pattern of check bits and writes them into the storage bits 112. Then, the data word and the generated check bits are read from the memory 104 by the EDC circuitry 100. The EDC circuitry 100 then uses the check bits to identify perceived errors in the data word. Such identified errors are then corrected. Thus, if the check bits are stored improperly, when the EDC circuitry 100 uses the erroneous check bits to identify any errors in the data word, the EDC circuitry 100 will improperly determine that the data word is erroneous; accordingly, the EDC circuitry 100 will modify the data word in accordance with the erroneous check bits. Thus, it is implied that if the EDC circuitry 100 supplies the CPU bus 102 with the same data word that was originally received from the CPU bus 102, the data word and the check bits were properly written to and read from the memory 104. Although this approach might be satisfactory for some purposes, many have found it to be inadequate. Particularly, calculating the required data word typically involves lengthy, laborious, and time-consuming operations. These operations are difficult since they must effectively accomplish the reverse process of the EDC circuitry 100 by calculating a data word based upon the desired check bits. Furthermore, this approach is limited since, if a memory error does occur, it is difficult to tell whether the error was associated with the data word, i.e. the storage bits 110, or the check bits, i.e. the storage bits 112.
Accordingly, a system is needed to directly test the check bits 112 of the memory 104. Furthermore, it would be beneficial if such a system did not introduce any delays into read operations of the computer.